urn:nasa:pds:orex.ocams:data_eng:20170928t000410s831_pol_ancil0_v001.dat 1.0 1.7.0.0 Product_Observational 2017-09-28T00:04:10.843Z 2017-09-28T02:35:57.413Z Engineering Raw OSIRIS-REx Mission urn:nasa:pds:context:investigation:mission.orex data_to_investigation OSIRIS-REx Camera Suite (OCAMS) OSIRIS-REx Spacecraft Origins, Spectral Interpretation, Resource Identification, Security - Regolith Explorer Spacecraft urn:nasa:pds:context:instrument_host:spacecraft.orex is_instrument_host OCAMS Instrument urn:nasa:pds:context:instrument:ocams.orex is_instrument Housekeeping Equipment 20170928T000410S831_pol_anciL0_V001.dat 2019-01-18T05:52:22.834Z 49210 0 190 Binary table of 162 fields of raw OCAMS housekeeping readings from the camera control module and image information telemetry packets taken at the same time as image acquisition. 162 0 259 data_type 1 1 UnsignedByte 1 %3d seconds_raw 2 2 UnsignedMSB4 4 %10d s Camera control module (CCM) seconds for start of exposure subseconds_raw 3 6 UnsignedMSB2 2 %5d Camera control module sub-seconds for start of exposure motor_pos 4 8 UnsignedMSB2 2 %5d Filter wheel or focus position mapcam_fwm_temp 5 10 UnsignedMSB2 2 %5d DN MapCam Filter Wheel Motor Thermistor mapcam_len_temp 6 12 UnsignedMSB2 2 %5d DN MapCam Lens Thermistor samcam_fwm_temp 7 14 UnsignedMSB2 2 %5d DN SamCam Filter Wheel Motor Thermistor samcam_len_temp 8 16 UnsignedMSB2 2 %5d DN SamCam Lens Thermistor polycam_fom_temp 9 18 UnsignedMSB2 2 %5d DN PolyCam Focus Motor Thermistor polycam_mirror_2_temp 10 20 UnsignedMSB2 2 %5d DN PolyCam Secondary Mirror Thermistor polycam_tbd_temp 11 22 UnsignedMSB2 2 %5d DN PolyCam TBD Thermistor mapcam_roe_temp 12 24 UnsignedMSB2 2 %5d DN MapCam Read Out Electronics Thermistor samcam_fwh_temp 13 26 UnsignedMSB2 2 %5d DN SamCam Filter Wheel Housing Thermistor samcam_roe_temp 14 28 UnsignedMSB2 2 %5d DN SamCam Read Out Electronics Thermistor mapcam_fwh_temp 15 30 UnsignedMSB2 2 %5d DN MapCam Filter Wheel Housing Thermistor polycam_roe_temp 16 32 UnsignedMSB2 2 %5d DN PolyCam Read Out Electronics Thermistor polycam_foh_temp 17 34 UnsignedMSB2 2 %5d DN PolyCam Focus Housing Thermistor polycam_mirror_1_temp 18 36 UnsignedMSB2 2 %5d DN PolyCam Primary Mirror Thermistor htr_test_pt 19 38 UnsignedMSB2 2 %5d DN Ground (Analog) htr_brd_temp 20 40 UnsignedMSB2 2 %5d DN Heater board temperature (unbuffered) dpu_brd_temp 21 42 UnsignedMSB2 2 %5d DN Digital processing unit (DPU) board temperature. lvps_brd_temp 22 44 UnsignedMSB2 2 %5d DN Low voltage power supply (LVPS) board temperature motor_brd_temp 23 46 UnsignedMSB2 2 %5d DN Motor Board Temperature cur_detector_minus_24 24 48 UnsignedMSB2 2 %5d DN -24 V current detector mapcam_ccd_temp 25 50 UnsignedMSB2 2 %5d DN MapCam CCD resistance temperature detector temperature samcam_ccd_temp 26 52 UnsignedMSB2 2 %5d DN SamCam CCD resistance temperature detector (RTD) temperature cur_detector_plus_24 27 54 UnsignedMSB2 2 %5d DN +24 V current detector cur_htr 28 56 UnsignedMSB2 2 %5d DN Heater Current cur_motor 29 58 UnsignedMSB2 2 %5d DN Motor Current cur_index 30 60 UnsignedMSB2 2 %5d DN Index Lamp Current cur_lamp 31 62 UnsignedMSB2 2 %5d DN Illumination Lamp Current volt_mon_sc 32 64 UnsignedMSB2 2 %5d DN Primary Voltage from S/C polycam_ccd_temp 33 66 UnsignedMSB2 2 %5d DN PolyCam CCD resistance temperature detector (RTD) temperature volt_mon_minus_24 34 68 UnsignedMSB2 2 %5d DN -24 V Monitor (buffered) volt_mon_minus_12 35 70 UnsignedMSB2 2 %5d DN -12 V Monitor volt_mon_plus_24 36 72 UnsignedMSB2 2 %5d DN +24 V Monitor volt_4_5_therm_mon_1 37 74 UnsignedMSB2 2 %5d DN +4.5 V Thermistor Monitor #1 volt_4_5_therm_mon_2 38 76 UnsignedMSB2 2 %5d DN +4.5 V Thermistor Monitor #2 volt_mon_plus_12 39 78 UnsignedMSB2 2 %5d DN +12 V Monitor volt_mon_plus_5 40 80 UnsignedMSB2 2 %5d DN +5 V Monitor vref_mon_plus_5 41 82 UnsignedMSB2 2 %5d DN +5 V Reference Monitor ground 42 84 UnsignedMSB2 2 %5d DN Ground (Analog) cur_detector_plus_5 43 86 UnsignedMSB2 2 %5d DN +5 V current detector adc_mode 44 88 UnsignedByte 1 %3d ADC readout mode: 1 equals averaged, 0 equals instant standby 45 89 UnsignedByte 1 %3d Bitwise non-Off state of the cameras: 1 equals MapCam, 2 equals SamCam, 4 equals PolyCam lut 46 90 UnsignedByte 1 %3d Currently selected LUT number: 0 equals None. The description of this field will be updated as more LUTS are added. active 47 91 UnsignedByte 1 %3d Camera number of active camera (1-Map, 2-Sam, 3-Poly). Note that the numeric values are different than those of the CAMERAID. motor_zone 48 92 UnsignedByte 1 %3d Width of the last home command’s index (greater than 31 is 31) reserved11 49 93 UnsignedMSB2 2 %5d Reserved index_led_read 50 95 UnsignedByte 1 %3d Bitwise read of the active LED sensors reserved12 51 96 UnsignedByte 1 %3d Reserved index_led_sel 52 97 UnsignedByte 1 %3d Camera number of the active motor index LED set motor_select 53 98 UnsignedByte 1 %3d Camera number of the active motor cal_lamp_sel 54 99 UnsignedByte 1 %3d Bitwise Camera of the active illumination lamp action_mode 55 100 UnsignedByte 1 %3d Action sequence enable mode: 0 equals off, 1 equals on eeprom_mode 56 101 UnsignedByte 1 %3d Reserved samcam_lens_heater 57 102 UnsignedByte 1 %3d State of the heater: 0 equals off, 1 equals on samcam_filt_house_heater 58 103 UnsignedByte 1 %3d State of the heater: 0 equals off, 1 equals on samcam_readout_elect_heater 59 104 UnsignedByte 1 %3d State of the heater: 0 equals off, 1 equals on samcam_ccd_heater 60 105 UnsignedByte 1 %3d SamCam CCD heater, on/off state mapcam_filt_motor_heater 61 106 UnsignedByte 1 %3d State of the heater: 0 equals off, 1 equals on mapcam_lens_heater 62 107 UnsignedByte 1 %3d State of the heater: 0 equals off, 1 equals on mapcam_filt_house_heater 63 108 UnsignedByte 1 %3d State of the heater: 0 equals off, 1 equals on mapcam_readout_elect_heater 64 109 UnsignedByte 1 %3d State of the heater: 0 equals off, 1 equals on samcam_filt_motor_heater 65 110 UnsignedByte 1 %3d State of the heater: 0 equals off, 1 equals on polycam_ccd_heater 66 111 UnsignedByte 1 %3d PolyCam CCD heater, on/off state polycam_tbd_heater 67 112 UnsignedByte 1 %3d State of the heater: 0 equals off, 1 equals on polycam_secondary_heater 68 113 UnsignedByte 1 %3d State of the heater: 0 equals off, 1 equals on polycam_focus_motor_heater 69 114 UnsignedByte 1 %3d State of the heater: 0 equals off, 1 equals on polycam_primary_heater 70 115 UnsignedByte 1 %3d State of the heater: 0 equals off, 1 equals on polycam_readout_elect_heater 71 116 UnsignedByte 1 %3d State of the heater: 0 equals off, 1 equals on polycam_focus_house_heater 72 117 UnsignedByte 1 %3d State of the heater: 0 equals off, 1 equals on mapcam_ccd_heater 73 118 UnsignedByte 1 %3d MapCam CCD heater, on/off state detector_mode 74 119 UnsignedByte 1 %3d Imaging command mode. checksum2 75 120 UnsignedMSB2 2 %5d Checksum of all data in CCM packet sync 76 122 UnsignedMSB2 2 %5d The sync pattern, always 0xED35 packet_id 77 124 UnsignedMSB2 2 %5d Packet identification number packet_len 78 126 UnsignedMSB2 2 %5d Packet length in bytes image_id 79 128 UnsignedMSB2 2 %5d Identifier that is associated with an image board_rev_num 80 130 UnsignedByte 1 %3d CCD board revision number fpga_rev_num 81 131 UnsignedByte 1 %3d FPGA revision number ccd_rev_num 82 132 UnsignedByte 1 %3d CCD revision number cam_info_reserved 83 133 UnsignedByte 1 %3d Reserved camera_id 84 134 UnsignedByte 1 %3d ID of camera in use. 0- Map, 1-Sam, 2-Poly. Note that the numeric values for ACTV_CAM are different, but the named camera will be identical. image_rows 85 135 UnsignedMSB2 2 %5d Number of CCD rows in image image_cols 86 137 UnsignedMSB2 2 %5d Number of CCD columns in image min_cnt 87 139 UnsignedMSB2 2 %5d min Number of minutes since reset int_time 88 141 UnsignedMSB4 4 %10d ms Commanded exposure time in milliseconds read_start 89 145 UnsignedMSB4 4 %10d Starting read address for a memory dump read_end 90 149 UnsignedMSB4 4 %10d Ending read address for a memory dump sdram_csr 91 153 UnsignedMSB2 2 %5d SDRAM Memory Control/Status Register: 0 equals off, 1 equals 0n flags 92 155 UnsignedMSB2 2 %5d Interface flags pwr_mon_vod_l_override 93 157 UnsignedByte 1 %3d Power monitor high-performance charge couple device (HCCD) drain override. Enable equals 1. pwr_mon_vdd_l_override 94 158 UnsignedByte 1 %3d Power monitor on-chip amplifier drain override. Enable equals 1. pwr_mon_wbb_l_override 95 159 UnsignedByte 1 %3d Power monitor substrate bias override. Enable equals 1. ccd_csr_reserved 96 160 UnsignedByte 1 %3d CCD control status register reserve bit ccd_rst_l_pulse 97 161 UnsignedByte 1 %3d CCD control status reg left reset pulse indicator. 1 equals 25 ns RST_L pulse , 0 equals 12.5 ns (Control/Status) Note: if ADC_INCLK equals 10 MHz, RST_L is forced to 12.5 ns. ccd_rst_r_pulse 98 162 UnsignedByte 1 %3d CCD control status reg right reset pulse indicator. 1 equals 25 ns RST_R pulse, 0 equals 12.5 ns (Control/Status) Note: if ADC_INCLK equals 10 MHz, RST_R is forced to 12.5 ns. encode_upper_pixel_bits 99 163 UnsignedByte 1 %3d Charge couple device control status register 1 equals encode upper pixel bits imgs_to_capture 100 164 UnsignedByte 1 %3d Number of images to capture (Control/Status) Minimum/Default equals 1; Maximum equals 28 storage_flush_block_flag 101 165 UnsignedByte 1 %3d Charge couple device control status register storage flush block flag. Enable equals 1. adc_clamp_enable 102 166 UnsignedByte 1 %3d Analog to digital converter clamp enable during imaging. Enable equals 1. readout_mode 103 167 UnsignedByte 1 %3d Readout mode of detector vfreq_csr 104 168 UnsignedMSB2 2 %5d CCD vertical clock frequency control, i.e., number of system clock cycles for each of the 8 vertical clock periods vcte_csr 105 170 UnsignedByte 1 %3d Vertical over scan count hcte_csr 106 171 UnsignedByte 1 %3d Horizontal over scan count cx_pattern 107 172 UnsignedMSB2 2 %5d CCD vertical clock pattern. There are 8 bit periods per vertical clock cycle. CX_PATT determines the high to low ratio incremented each VFREQCSR count cycle. storage_flush_cnt 108 174 UnsignedMSB2 2 %5d ms Milliseconds between storage portion flushes cs1h_ccd 109 176 UnsignedMSB2 2 %5d CCD Storage clock pattern. CCD Storage clock patterns during a storage to horizontal register transfer. There are 8 bit periods per storage clock cycle. The CS1H_CCD determines the high to low ratio incremented each VFREQCSR count cycle. cs2h_ccd 110 178 UnsignedMSB2 2 %5d CCD Storage clock pattern. CCD Storage clock patterns during a storage to horizontal register transfer. There are 8 bit periods per storage clock cycle. The CS2H_CCD determines the high to low ratio incremented each VFREQCSR count cycle. cs3h_ccd 111 180 UnsignedMSB2 2 %5d CCD Storage clock patterns during a storage to horizontal register transfer. There are 8 bit periods per storage clock cycle. The CS3H_CCD determines the high to low ratio incremented each VFREQCSR count cycle. cs4h_ccd 112 182 UnsignedMSB2 2 %5d CCD Storage clock patterns during a storage to horizontal register transfer. There are 8 bit periods per storage clock cycle. The CS4H_CCD determines the high to low ratio incremented each VFREQCSR count cycle. tck_pattern 113 184 UnsignedMSB2 2 %5d CCD transfer clock pattern. There are 8 bit periods per the clock cycle. TCK_PATTERN determines the high to low ratio. main_config 114 186 UnsignedByte 1 %3d Main configuration power_control 115 187 UnsignedByte 1 %3d Power down control pga_power_trim 116 188 UnsignedByte 1 %3d PGA Power Trimming Register adc_power_trim 117 189 UnsignedByte 1 %3d ADC Power Trimming Register voltage_control 118 190 UnsignedByte 1 %3d Voltage Clamp Buffer Control Register lvds_config 119 191 UnsignedByte 1 %3d LVDS Output Configuration Register sample_hold 120 192 UnsignedByte 1 %3d Sample and Hold Mode Register status_reg 121 193 UnsignedByte 1 %3d Status Register reserved1 122 194 UnsignedBitString 6 Reserved chan1_course_dac_reg_unused 123 200 UnsignedByte 1 %3d Unused register chan1_course_dac_reg_val 124 201 UnsignedMSB2 2 %5d Channel 1 coarse DAC register. 0 equals off, 1 equals on. chan1_fine_dac_reg_unused 125 203 UnsignedByte 1 %3d Unused register chan1_fine_dac_reg_val 126 204 UnsignedMSB2 2 %5d Channel 1 fine DAC register. 0 equals off, 1 equals on. reserved2 127 206 UnsignedByte 1 %3d Reserved pga1_gain_amp 128 207 UnsignedByte 1 %3d DN Channel 1 Programmable Gain Amplifier Value reserved3 129 208 UnsignedMSB2 2 %5d Reserved chan2_course_dac_reg_unused 130 210 UnsignedByte 1 %3d Unused register chan2_course_dac_reg_val 131 211 UnsignedMSB2 2 %5d Channel 2 coarse DAC register. 0 equals off, 1 equals on. chan2_fine_dac_reg_unused 132 213 UnsignedByte 1 %3d Unused register chan2_fine_dac_reg_val 133 214 UnsignedMSB2 2 %5d Channel 2 fine DAC register. 0 equals off, 1 equals on. pga2_gain_amp 134 216 UnsignedByte 1 %3d DN Channel 2 Programmable Gain Amplifier Value reserved4 135 217 UnsignedBitString 3 Reserved clamp_start_reg_unused 136 220 UnsignedByte 1 %3d Unused register clamp_start_reg_val 137 221 UnsignedByte 1 %3d Clamp Start Register clamp_end_reg_unused 138 222 UnsignedByte 1 %3d Unused register clamp_end_reg_val 139 223 UnsignedByte 1 %3d Clamp End Register sample_start_reg_unused 140 224 UnsignedByte 1 %3d Unused register sample_start_reg_val 141 225 UnsignedByte 1 %3d Sample Start Register sample_end_reg_unused 142 226 UnsignedByte 1 %3d Unused register sample_end_reg_val 143 227 UnsignedByte 1 %3d Sample End Register reserved5 144 228 UnsignedByte 1 %3d Reserved inclk_range_register 145 229 UnsignedByte 1 %3d Internal Clock Range Register reserved6 146 230 UnsignedMSB2 2 %5d Reserved dll_config_reg 147 232 UnsignedByte 1 %3d DLL Configuration Register reserved7 148 233 UnsignedBitString 7 Reserved test_scan_cntrl 149 240 UnsignedByte 1 %3d Test and Scan Control Register device_id 150 241 UnsignedByte 1 %3d Analog to digital converter device revision identifier reserved8 151 242 UnsignedByte 1 %3d Reserved clock_mon_reg 152 243 UnsignedByte 1 %3d Internal Clock Signal Monitor Register test_start 153 244 UnsignedMSB2 2 %5d Test Pattern start value test_width 154 246 UnsignedMSB2 2 %5d Test Pattern width value test_pitch 155 248 UnsignedByte 1 %3d Test Pattern pitch test_step 156 249 UnsignedByte 1 %3d Test Pattern step code test_ch_offset 157 250 UnsignedByte 1 %3d Test Pattern Channel Offset Register digital_config 158 251 UnsignedByte 1 %3d Serial Communication Configuration Register test_value 159 252 UnsignedMSB2 2 %5d Test Pattern Value Register reserved9 160 254 UnsignedBitString 3 Reserved test_cntrl 161 257 UnsignedByte 1 %3d Test Pattern Control Register checksum1 162 258 UnsignedMSB2 2 %5d Checksum over sum of all data in ID packet